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14 February 2018

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module lab5part2(SW, CLOCK_50, HEX0, HEX1);
input [2:0] SW;
input CLOCK_50;
output [6:0] HEX0;
output [6:0] HEX1;

main m1(
.Select(SW[1:0]),
.Reset(SW[2]),
.Clock(CLOCK_50),
.HEX0(HEX0),
.HEX1(HEX1));

endmodule

module main(Select, Reset, Clock, HEX0, HEX1);
input [1:0] Select;
input Reset;
input Clock;
output [6:0] HEX0;
output [6:0] HEX1;

wire RD_out;
wire [7:0] DC_out;


RateDivider r1(
.Clock(Clock),
.Select(Select),
.Reset(Reset),
.Out(RD_out)
);

DisplayCounter d1(
.Clock(Clock),
.Enable(RD_out),
.Reset(Reset),
.Q(DC_out)
);

decoder de0(
.I(DC_out[3:0]),
.HEX(HEX0));
decoder de1(
.I(DC_out[7:4]),
.HEX(HEX1));
endmodule // main

module DisplayCounter(Clock, Enable, Reset, Q);
input Clock;
input Enable;
input Reset;
output reg [7:0] Q;


always @(posedge Clock)
begin
if (Reset == 1'b1)
Q <= 0;
else if (Enable == 1'b1)
Q <= Q + 1;
// Overflow results in a value of 0000_0000 which is what we want so we don't care about it
end
endmodule


module RateDivider(Clock, Select, Reset, Out);
input Clock;
input [1:0] Select;
input Reset;
output Out;

reg [31:0] Counter;

assign Out = (Counter == 32'b0000_0000_0000_0000_0000_0000_0000_0001) ? 1 : 0; // Since it changes instantly when 0 back to max
always @(posedge Clock)
begin
if (Counter == 32'b0000_0000_0000_0000_0000_0000_0000_0000 || Reset == 1'b1)
begin
if (Select == 2'b00)
Counter <= 1;
else if (Select == 2'b01)
Counter <= 32'b0000_0010_1111_1010_1111_0000_1000_0000; // 1 Hz
else if (Select == 2'b10)
Counter <= 32'b000_0010_1111_1010_1111_0000_1000_0000_0; // 0.5 Hz
else if (Select == 2'b11)
Counter <= 32'b00_0010_1111_1010_1111_0000_1000_0000_00; // 0.25 Hz
end
else
Counter <= Counter - 1'b1;
end
endmodule

module decoder(I, HEX);
input [3:0] I;
output [6:0] HEX;


// default minterm is (I[0] & I[1] & I[2] & I[3])
assign HEX[0] = (I[0] & ~I[1] & ~I[2] & ~I[3]) | (~I[0] & ~I[1] & I[2] & ~I[3]) | (I[0] & I[1] & ~I[2] & I[3]) | (I[0] & ~I[1] & I[2] & I[3]);
assign HEX[1] = (I[0] & ~I[1] & I[2] & ~I[3]) | (~I[0] & I[2] & I[3]) | (I[1] & I[2] & I[3]) | (~I[0] & I[1] & I[2]) | (I[0] & I[1] & I[3]);
assign HEX[2] = (~I[0] & I[1] & ~I[2] & ~I[3]) | (I[1] & I[2] & I[3]) | (~I[0] & I[2] & I[3]);
assign HEX[3] = (~I[0] & ~I[1] & I[2] & ~I[3]) | (I[0] & ~I[1] & ~I[2]) | (I[0] & I[1] & I[2]) | (~I[0] & I[1] & ~I[2] & I[3]);
assign HEX[4] = (I[0] & ~I[3]) | (I[0] & ~I[1] & ~I[2]) | (~I[1] & I[2] & ~I[3]);
assign HEX[5] = (I[0] & ~I[1] & I[2] & I[3]) | (I[0] & ~I[2] & ~I[3]) | (I[1] & ~I[2] & ~I[3]) | (I[0] & I[1] & ~I[3]);
assign HEX[6] = (~I[1] & ~I[2] & ~I[3]) | (I[0] & I[1] & ~I[3]) | (~I[0] & ~I[1] & I[2] & I[3]);

endmodule

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