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14 February 2018

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module lab5part3(SW, KEY, CLOCK_50, LEDR);
input [2:0] SW;
input [1:0] KEY;
input CLOCK_50;
output [1:0] LEDR;

main m0(
.Select(SW),
.Reset(KEY[0]),
.Load(KEY[1]),
.Clock(CLOCK_50),
.Out(LEDR[0]));
endmodule

module main(Select, Reset, Load, Clock, Out);
input [2:0] Select;
input Reset;
input Load;
input Clock;
output Out;

wire output_of_rate_divider;
// """"temporary"""" name

reg [13:0] to_load;
reg [13:0] ShiftQueue;
assign Out = ShiftQueue[13];

always @(*) // the LUT
begin
case (Select[2:0])
3'b000: to_load = 14'b10101000000000;
3'b001: to_load = 14'b11100000000000;
3'b010: to_load = 14'b10101110000000;
3'b011: to_load = 14'b10101011100000;
3'b100: to_load = 14'b10111011100000;
3'b101: to_load = 14'b11101010111000;
3'b110: to_load = 14'b11101011101110;
3'b111: to_load = 14'b11101110100000;
endcase // case (Select[2:0])

end // always

always @(posedge output_of_rate_divider, posedge Reset)
begin
if (Load)
ShiftQueue <= to_load;
else if (Reset)
ShiftQueue <= 14'b00000000000000;
else
ShiftQueue <= ShiftQueue 1'b1;
end


RateDivider rd0(
.Clock(Clock),
.Reset(Reset),
.Out(output_of_rate_divider));

endmodule

module RateDivider(Clock, Reset, Out);
input Clock;
input Reset;
output Out;

reg [31:0] Counter;

assign Out = (Counter == 32'b0000_0000_0000_0000_0000_0000_0000_0001) ? 1 : 0; // Since it changes instantly when 0 back to max
always @(posedge Clock)
begin
if (Counter == 32'b0000_0000_0000_0000_0000_0000_0000_0000 || Reset == 1'b1)
begin
Counter <= 32'b00000_0010_1111_1010_1111_0000_1000_000; // 2 Hz
end
else
Counter <= Counter - 1'b1;
end
endmodule

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