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14 February 2018

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module lab5part1(SW, KEY, HEX0, HEX1);
input [2:0] SW;
input KEY;
output [6:0] HEX0;
output [6:0] HEX1;

wire [7:0] Q_out;


main m1(
.Enable(SW[1] ),
.Clock(KEY),
.Clear_b(SW[0]),
.Q(Q_out));

decoder d1(
.I(Q_out[3:0]),
.HEX(HEX0));
decoder d2(
.I(Q_out[7:4]),
.HEX(HEX1));


endmodule

module main(Enable, Clock, Clear_b, Q);
input Enable;
input Clock;
input Clear_b;

output [7:0] Q;


TFlipFlop TFF0(
.T(Enable),
.Clock(Clock),
.Clear_b(Clear_b),
.Q(Q[0])
);
TFlipFlop TFF1(
.T(Enable & Q[0]),
.Clock(Clock),
.Clear_b(Clear_b),
.Q(Q[1])
);
TFlipFlop TFF2(
.T(Enable & Q[0] & Q[1]),
.Clock(Clock),
.Clear_b(Clear_b),
.Q(Q[2])
);
TFlipFlop TFF3(
.T(Enable & Q[0] & Q[1] & Q[2]),
.Clock(Clock),
.Clear_b(Clear_b),
.Q(Q[3])
);
TFlipFlop TFF4(
.T(Enable & Q[0] & Q[1] & Q[2] & Q[3]),
.Clock(Clock),
.Clear_b(Clear_b),
.Q(Q[4])
);
TFlipFlop TFF5(
.T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4]),
.Clock(Clock),
.Clear_b(Clear_b),
.Q(Q[5])
);
TFlipFlop TFF6(
.T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5]),
.Clock(Clock),
.Clear_b(Clear_b),
.Q(Q[6])
);
TFlipFlop TFF7(
.T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5] & Q[6]),
.Clock(Clock),
.Clear_b(Clear_b),
.Q(Q[7])
);
endmodule

module TFlipFlop(T, Q, Clock, Clear_b);
input T;
input Clock;
input Clear_b;

output reg Q;

always @(posedge Clock, negedge Clear_b)
begin
if (Clear_b == 0)
Q <= 0;
else if (T == 1)
Q <= ~Q;
end
endmodule

module decoder(I, HEX);
input [3:0] I;
output [6:0] HEX;


// default minterm is (I[0] & I[1] & I[2] & I[3])
assign HEX[0] = (I[0] & ~I[1] & ~I[2] & ~I[3]) | (~I[0] & ~I[1] & I[2] & ~I[3]) | (I[0] & I[1] & ~I[2] & I[3]) | (I[0] & ~I[1] & I[2] & I[3]);
assign HEX[1] = (I[0] & ~I[1] & I[2] & ~I[3]) | (~I[0] & I[2] & I[3]) | (I[1] & I[2] & I[3]) | (~I[0] & I[1] & I[2]) | (I[0] & I[1] & I[3]);
assign HEX[2] = (~I[0] & I[1] & ~I[2] & ~I[3]) | (I[1] & I[2] & I[3]) | (~I[0] & I[2] & I[3]);
assign HEX[3] = (~I[0] & ~I[1] & I[2] & ~I[3]) | (I[0] & ~I[1] & ~I[2]) | (I[0] & I[1] & I[2]) | (~I[0] & I[1] & ~I[2] & I[3]);
assign HEX[4] = (I[0] & ~I[3]) | (I[0] & ~I[1] & ~I[2]) | (~I[1] & I[2] & ~I[3]);
assign HEX[5] = (I[0] & ~I[1] & I[2] & I[3]) | (I[0] & ~I[2] & ~I[3]) | (I[1] & ~I[2] & ~I[3]) | (I[0] & I[1] & ~I[3]);
assign HEX[6] = (~I[1] & ~I[2] & ~I[3]) | (I[0] & I[1] & ~I[3]) | (~I[0] & ~I[1] & I[2] & I[3]);

endmodule

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